Apparatuses and methods to control body potential in 3d non-volatile memory operations

ABSTRACT

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.16/228,733, filed Dec. 20, 2018, which is a continuation of U.S.application Ser. No. 15/849,267, filed Dec. 20, 2017, now issued as U.S.Pat. No. 10,170,196, which is a continuation of U.S. application Ser.No. 15/393,719, filed Dec. 29, 2016, now issued as U.S. Pat. No.9,881,686, which is a continuation of U.S. application Ser. No.14/746,416, filed Jun. 22, 2015, now issued as U.S. Pat. No. 9,536,618,which is a divisional of U.S. application Ser. No. 13/707,067, filedDec. 6, 2012, now issued as U.S. Pat. No. 9,064,577, all of which areincorporated herein by reference in their entireties.

BACKGROUND

Memory devices, such as flash memory, are widely used in computers andmany electronic items. Such memory devices have numerous memory cells.Information can be stored in the memory cells in a write operation. Thestored information can be obtained in a read operation or can be clearedin an erase operation. Some conventional read, write, and eraseoperations may generate excess carriers (e.g., electrons or holes) insome areas of the memory device. In some situations, such excesscarriers may affect the reliability of these operations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice having a memory array and memory cells, according to anembodiment of the invention.

FIG. 2A shows a schematic diagram of a portion of a memory deviceincluding a memory array having memory blocks and including a resetcircuit, according to an embodiment of the invention.

FIG. 2B shows a side view of a structure of a portion of the memorydevice of FIG. 2A, according to an embodiment of the invention.

FIG. 3 shows a diagram illustrating different stages of a writeoperation of the memory device of FIG. 2A and FIG. 2B, according to anembodiment of the invention.

FIG. 4 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during the write operationshown in FIG. 3, according to an embodiment of the invention.

FIG. 5 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during a reset stage, accordingto an embodiment of the invention.

FIG. 6 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during an alternative resetstate, according to an embodiment of the invention.

FIG. 7 shows a diagram illustrating different stages of an alternativewrite operation of the memory device of FIG. 2A and FIG. 2B, accordingto an embodiment of the invention.

FIG. 8 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during the write operationshown in FIG. 7, according to an embodiment of the invention.

FIG. 9 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during another alternativewrite operation, according to an embodiment of the invention.

FIG. 10 shows a diagram illustrating different stages of read operationof the memory device of FIG. 2A and FIG. 2B, according to an embodimentof the invention.

FIG. 11A is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during the read operation ofFIG. 10, according to an embodiment of the invention.

FIG. 11B is an alternative timing diagram showing waveforms of some ofthe signals of the memory device of FIG. 2A and FIG. 2B during the readoperation of FIG. 10, according to an embodiment of the invention.

FIG. 12 is a timing diagram showing waveforms of some of the signals ofthe memory device of FIG. 2A and FIG. 2B during an alternative readoperation, according to an embodiment of the invention.

FIG. 13 shows a diagram illustrating different stages of an eraseoperation of the memory device of FIG. 2A and FIG. 2B, according to anembodiment of the invention.

FIG. 14 is a flowchart for a method of performing an operation (e.g.,read, write, or erase) in a device, according to an embodiment of theinvention.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice 100 having a memory array 101 and memory cells 103, according toan embodiment of the invention. Memory cells 103 can be arranged in rowsand columns along with lines 150 and lines 170. Lines 150 can carrysignals WL0 through WLm and can form part of access lines (e.g., wordlines) of memory device 100. Lines 170 can carry signals BL0 through BLnand can form part of data lines (e.g., bit lines) of memory device 100.

A row decoder 108 and a column decoder 109 can respond to an addressregister 112 to access memory cells 103 based on row address and columnaddress signals on lines 110, 111, or both. A sense amplifier 175 canoperate to determine the values of information to be stored in memorycells 103 or the values of information obtained from memory cells 103.Sense amplifier 175 can respond to signals SLE1 through SLEn toselectively provide information between memory cells 103 an input/output(I/O) circuit 114. I/O circuit 114 can be configured to exchangeinformation (e.g., provide signals) between sense amplifier 175 andlines 110. Lines 110 and 111 can include nodes within memory device 100or pins (or solder balls) on a package where memory device 100 islocated.

A memory control unit 116 can control operations of memory device 100based on signals present on lines 110 and 111. A device (e.g., aprocessor or a memory controller) external to memory device 100 can senddifferent commands (e.g., read, write, or erase command) to memorydevice 100 using different combinations of signals on lines 110, 111, orboth.

Memory device 100 can respond to commands to perform memory operationson memory cells 103. For example, memory device 100 can perform a readoperation to determine the value of information stored in memory cells103 and a write (e.g., programming) operation to store (e.g., program)information in memory cells 103. Memory device 100 can also perform anerase operation to erase information from some or all of memory cells103.

Memory device 100 can receive a supply voltage, including supplyvoltages Vcc and Vss. Supply voltage Vss can operate at a groundpotential (e.g., having a value of approximately zero volts). Supplyvoltage Vcc can include an external voltage supplied to memory device100 from an external power source such as a battery or analternating-current to direct-current (AC-DC) converter circuitry.Memory device 100 can include a voltage generator 107 to generatevoltages for use in operations of memory device 100, such as in read,write, and erase operations. Voltage generator 107 can include chargepumps, such as positive charge pumps (e.g., to provide pumped voltageshaving positive values) and negative charge pumps (e.g., to providepumped voltage having negative values).

Memory device 100 can include a reset circuit 195 that can respond to asignal RESET to apply certain voltages to different elements (e.g.,lines 150 and 170) of memory device 100 at specific stages of a memoryoperation (e.g., read, write, or erase) of memory device 100. Memoryoperations including different stages are described in more detail withreference to FIG. 2A through FIG. 14.

FIG. 1 shows reset circuit 195 being separated from other elements ofmemory device 200 as an example. A portion of reset circuit 195 or theentire reset circuit 195, however, can be part of another element or caninclude part of another element of memory device 100. For example, aportion of reset circuit 195 or the entire reset circuit 195 can be partof memory control unit 116 or other elements of memory device 100.

Each of memory cells 103 can be programmed to store informationrepresenting a value of a fraction of a bit, a value of a single bit, ora value of multiple bits such as two, three, four, or another number ofbits. For example, each of memory cells 103 can be programmed to storeinformation representing a binary value “0” or “1” of a single bit. Thesingle bit per cell is sometimes called a single level cell. In anotherexample, each of memory cells 103 can be programmed to store informationrepresenting a value for multiple bits, such as one of four possiblevalues “00,” “01,” “10,” and “11” of two bits, one of eight possiblevalues “000,” “001,” “010,” “011,” “100,” “101,” “110,” and “111” ofthree bits, or one of other values of another number of multiple bits. Acell that has the ability to store multiple bits is sometimes called amulti-level cell (or multi-state cell).

Memory device 100 can include a non-volatile memory device, and memorycells 103 can include non-volatile memory cells, such that memory cells103 can retain information stored in them when power (e.g., Vcc, Vss. orboth) is disconnected from memory device 100. For example, memory device100 can be a flash memory device, such as a NAND flash or a NOR flashmemory device, or another kind of memory device, such as a variableresistance memory device (e.g., a phase change or resistive randomaccess memory (RAM) device).

Memory device 100 can include a memory device where memory cells 103 canbe physically located in multiple levels on the same device, such thatsome of memory cells 103 can be stacked over some other memory cells 103in multiple levels over a substrate (e.g., a semiconductor substrate) ofmemory device 100.

One of ordinary skill in the art may recognize that memory device 100may include other elements, several of which are not shown in FIG. 1, soas not to obscure the example embodiments described herein.

At least a portion of memory device 100 can include structures andoperate using memory operations (e.g., read, write, and eraseoperations) similar to or identical to memory devices described belowwith reference to FIG. 2A through FIG. 14.

FIG. 2A shows a schematic diagram of a portion of a memory device 200including a memory array 201 having memory blocks 203 ₀ and 203 ₁, andincluding reset circuit 295, according to an embodiment of theinvention. FIG. 2A shows memory device 200 and memory array 201including two memory blocks 203 ₀ and 203 ₁ as an example. The number ofmemory blocks in memory device 200 can vary.

Memory device 200 can include lines 270, 271, and 272 that can carrysignals BL0, BL1, and BL2, respectively. Lines 270, 271, and 272 cancorrespond to lines 170 of FIG. 1. Each of lines 270, 271, and 272 canbe structured as a conductive line and can form part of a respectivedata line of memory device 200. Memory device 200 can include line 291,which can be structured as a conductive line and can form part of asource (e.g., a source line) of memory device 200. Line 291 can carry asignal, such as signal SRC (e.g., source line signal). Memory blocks 203₀ and 203 ₁ can share the same lines 270, 271, 272, and 291. FIG. 2Ashows three lines (e.g., data lines) 270, 271, and 272 as an example.The number of such lines can vary.

Reset circuit 295 of memory device 200 can correspond to reset circuit195 of FIG. 1. Reset circuit 295 can be configured to respond to signalRESET in order to apply (e.g., couple) certain voltages to some or allof lines 270, 271, 272, and 291 at specific time intervals in memoryoperations (e.g., read, write, and erase) of memory device 200, asdescribed in more detail below with reference to FIG. 3 through FIG. 14.

As shown in FIG. 2A, memory blocks 203 ₀ and 203 ₁ can include similaror identical elements. Each of memory blocks 203 ₀ and 203 ₁ can includerespective control gates 250, 251, 252, and 253 that can carryrespective signals WL0 ₀, WL1 ₀, WL2 ₀, and WL3 ₀ and signals WL0 ₁, WL1₁, WL2 ₁, and WL3 ₁. Each of control gates 250, 251, 252, and 253 canform part of a respective access line of memory device 200 that can besimilar to one of lines 150 of FIG. 1. FIG. 2A shows four control gates250, 251, 252, and 253 in each of memory blocks 203 ₀ and 203 ₁ as anexample. The number of such control gates can vary.

Each of memory blocks 203 ₀ and 203 ₁ can include memory cells 210, 211,212, and 213 and transistors (e.g., select transistors) 261, 262, 263,and 264 that can be arranged in memory cell strings, such as memory cellstrings 231, 232, and 233. For simplicity, in FIG. 2A, only three of thememory cell strings are labeled (231, 232, and 233).

Each of the memory cell strings (e.g., 231, 232, and 233) can includememory cells 210, 211, 212, and 213 and transistors (e.g., selecttransistors) coupled between line 291 and one of lines 270, 271, and272. For example, memory cell string 231 can include memory cells 210,211, 212, and 213, transistor 264 (immediately above memory cell 213),and transistor 262 (immediately below memory cell 210) coupled betweenline 291 and line 270.

Some memory cells in the same memory block can share the same controlgate. For example, in memory blocks 203 ₀, memory cells 210 can sharethe same control gate 250, memory cells 211 can share the same controlgate 251.

FIG. 2A shows an example where each of memory blocks 203 ₀ and 203 ₁ caninclude six memory cell strings and four memory cells 210, 211, 212, and213 in each memory cell string. The number of memory cell strings in ablock and the number of memory cells in each memory cell string canvary.

As shown in FIG. 2A, in each of memory blocks 203 ₀ and 203 ₁,transistors 261 and 262 can be associated with (e.g., can share) thesame select gate 280. Select gate 280 can form part of a select line(e.g., source select line) of memory device 200. Transistors 261 and 262can be controlled (e.g., turned on or turned off) by the same signal,such as an SGS₀ signal or SGS₁ (e.g., source select gate signal)associated with select gate 280. For example, during a memory operation(e.g., such as a read or write operation) in memory blocks 203 ₀,transistors 261 and 262 can be turned on (e.g., by activating signalSGS₀) to couple the memory cell strings of memory device 200 to a line291. Transistors 261 and 262 can be turned off (e.g., by deactivatingthe SGS₀ signal) to decouple the memory cell strings of memory device200 from line 291.

Transistors 263 and 264 in each of memory blocks 203 ₀ and 203 ₁ can beassociated with separate select gates (e.g., drain select gates) 285 and286. However, transistors 263 in the same memory block can be associatedwith the same select gate 285 (e.g., can share the same select gate 285)in that memory block. Transistors 264 in the same memory block can beassociated with the same select gate 286 (e.g., can share the sameselect gate 286) in that memory block. Each of select gates 285 and 286can form part of a respective select line (e.g., drain select line) ofmemory device 200.

Transistors 263 and 264 memory blocks 203 ₀ and 203 ₁ can be controlled(e.g., turned on or turned off) by corresponding signals (e.g., drainselect gate signals) SGD0 ₀, SGD1 ₀, SGD0 ₁, SGD1 ₁, in order toselectively couple the memory cell strings of memory device 200 to theirrespective lines 270, 271, and 272, during a memory operation, such as aread or write operation. For example, during a memory operation, ifmemory block 203 ₀ is selected, memory block 203 ₁ is unselected, andmemory cell string 231 is selected, then signal SGD1 ₀ can be activatedto couple memory cell string 231 to line 270. Signal SGD0 ₀ can bedeactivated to decouple the other memory cell strings (e.g., stringsincluding transistors 261 and 263) from lines 270, 271, and 272. Duringa memory operation (e.g., a read or write operation), only one of memoryblocks 203 ₀ and 203 ₁ can be selected at a time and only one of signalsSGD0 ₀, SGD1 ₀, SGD0 ₁, SGD1 ₁ in the selected memory block can beactivated at a time.

A selected memory block refers to the memory block that has at least onememory cell selected to store information in that memory cell (e.g., ina write operation) or to obtain information stored in that memory cell(e.g., in a read operation). A selected memory cell string refers to thememory cell string that includes the selected memory cell. An unselectedmemory cell string refers to the memory cell string having no selectedmemory cells. An unselected memory block refers to the memory blockhaving no selected memory cells.

FIG. 2B shows a side view of a structure of a portion of memory device200 of FIG. 2A, according to an embodiment of the invention. As shown inFIG. 2B, memory device 200 can include a substrate 290 where memory cellstring 231 can be formed over substrate 290. Substrate 290 can include asemiconductor material (e.g., silicon). Other memory cell strings ofmemory device 200 have structures similar to the structure of memorycell string 231.

As shown in FIG. 2B, memory cells 210, 211, 212, and 213 can be locatedin different levels 221, 222, 223, and 224, respectively, in az-direction of device 200. The z-direction can extend in a directionassociated with the thickness of substrate 290. FIG. 2B also shows anx-direction, which is perpendicular to the z-direction.

Memory cell string 231 can include a body 240 coupled to line 270. Line270 can include a conductive material (e.g., conductively dopedpolycrystalline silicon or other conductive material). Body 240 caninclude portion 241 coupled to line 270, a portion 242 coupled to line291, and a portion 243 between portions 241 and 242. Body 240 can have apillar structure extending outwardly from substrate 290 in thez-direction. Body 240 can include a conductive material that is capableof providing a conduction of current between lines 270 and 291. Portions241 and 242 can include materials of the same conductivity type. Portion243 can include a material of conductivity type different from that ofportions 241 and 242. For example, portions 241 and 242 can include asemiconductor material of n-type, and portion 243 can include asemiconductor material of p-type. In another example, portions 241 and242 can include a semiconductor material of p-type, and portion 243 caninclude a semiconductor material of n-type. The semiconductor materialsin portions 241, 242, and 243 can include polycrystalline silicon.

As shown in FIG. 2B, portions 241 and 243 can directly contact eachother and form a junction (e.g., p-n junction) 244. Portions 242 and 243can directly contact each other and form a junction (e.g., p-n junction)245. Each of junctions 244 and 245 can enable a flow of electrons orholes across the junction.

Each of memory cells 210, 211, 212, and 213 can surround or partiallysurround the body 240. Control gates 250, 251, 252, and 253 associatedwith memory cells 210, 211, 212, and 213 can be located along body 240in the z-direction. Each of control gates 250, 251, 252, and 253 cansurround or partially surround body 240. The materials of control gates250, 251, 252, and 253 can include a conductive material (e.g.,conductively doped polycrystalline silicon or other conductivematerial).

Memory cell string 231 can include materials 203, 204, and 205 betweenbody 240 and each of control gates 250, 251, 252, and 253. Material 205can also be between body 240 and each of select gates 280 and 286.Materials 203, 204, and 205 can be separated (e.g., in the z-direction)among memory cells 210, 211, 212, and 213.

Material 203 can include a charge blocking material(s) (e.g., adielectric material such as silicon nitride) that is capable of blockinga tunnel of a charge (e.g., electrons).

Material 204 can include a charge storage (e.g., charge trap)material(s) that can provide a charge storage function to represent avalue of information stored in memory cell 210, 211, 212, or 213. Forexample, material 204 can include conductively doped polycrystallinesilicon, which can be either a p-type polycrystalline silicon or ann-type polycrystalline silicon. The polycrystalline silicon can beconfigured to operate as a floating gate (e.g., to store charge) in amemory cell (e.g., memory cell 210, 211, 212, or 213). In anotherexample, material 204 can include a charge trap material(s) such assilicon nitride.

Material 205 can include a tunnel dielectric material(s) (e.g., an oxideof silicon) that is capable of allowing tunneling of a charge (e.g.,electrons).

Line 291 can be formed over a portion of substrate 290. Line 291 andportion 242 of body 240 can include materials of the same conductivitytype. FIG. 2B shows line 291 formed over substrate 290 (e.g., formed asseparate layer) as an example. Alternatively, line 291 can be formed ina portion of substrate 290. For example, line 291 can be formed as adoped region in substrate 290.

FIG. 3 shows a diagram illustrating a write stage 315, a reset stage316, a write verify stage 317, and another reset stage 316 of a writeoperation 310 of memory device 200 of FIG. 2A and FIG. 2B, according toan embodiment of the invention. The following description refers to FIG.2A, FIG. 2B, and FIG. 3. Memory device 200 can perform write stage 315,reset stage 316, write verify stage 317, and reset stage 316 in asequential order with respect to time (as shown in FIG. 3). In writestage 315, memory device 200 (FIG. 2A) can store information in aselected memory cell among memory cells 210, 211, 212, and 213 of amemory cell string, such as memory cell string 231. In write verifystage 317 (FIG. 3), memory device 200 can determine whether the value ofinformation stored in the selected memory cell (stored by write stage315) reaches a target value. The target value refers to a value ofinformation intended to be stored in a selected memory cell. The valueof information stored in a selected memory cell can be based on a state(e.g., threshold voltage) of the selected memory cell.

Reset stage 316 can be performed during a time interval between writestage 315 and write verify stage 317 and/or can also be performed afterwrite verify stage 317. For example, memory device 200 can be configuredto bypass reset stage 316 in write operation 310. However, as describedin more detail below with reference to FIG. 5 and FIG. 6, includingreset stage 316 in write operation 310 (FIG. 3) may improve thereliability of memory device 200.

As shown in FIG. 3, signal RESET can have different levels (e.g.,associated with different voltages) V_(DISABLE) and V_(ENABLE). LevelV_(DISABLE) can have a value (e.g., zero volts) less the value of levelV_(ENABLE). Memory device 200 can be configured to perform reset stage316 when signal RESET has level V_(ENABLE). Memory device 200 (FIG. 2A)can be configured to bypass reset stage 316 (between write stage 315 andwrite verify stage 317) and perform write verify stage 317 immediatelyafter write stage 315 if signal RESET has level V_(DISABLE) during atime interval between stages 315 and 317. For example, if signal RESEThas the same level V_(DISABLE) from time 398 to time 399, then resetstage 316 can be bypassed. Alternatively or additionally, memory device200 can be configured to bypass reset stage 316 after write verify stage317 is performed. For example, if signal RESET has the same levelV_(DISABLE) after time 399, then reset stage 316 after time 399 can bebypassed.

FIG. 4 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during write operation 310 ofFIG. 3, according to an embodiment of the invention. In FIG. 4, stages315, 316, and 317 correspond to those shown in FIG. 3. The signals(e.g., WL0 ₀, WL1 ₁, WL2 ₁, and WL3 ₁) in FIG. 4 correspond to the samesignals shown in FIG. 2A. The following description refers to FIG. 2A.FIG. 2B, FIG. 3, and FIG. 4.

In write operation 310 (FIG. 3 and FIG. 4), memory block 203 ₀ (FIG. 2A)is assumed to be a selected memory block and memory block 203 ₁ isassumed to be an unselected memory block. Memory cell 211 of memory cellstring 231 is assumed to be a selected memory cell. Thus, memory cellstring 231 can be a selected memory cell string. Control gate 251 of theselected block (associated with signal WL1 ₀) can be a selected controlgate. Control gates 250, 252, and 253 of the selected block (associatedwith signals WL0 ₀, WL2 ₀, and WL3 ₀) can be unselected control gates.Select gate 286 of the selected block (associated with correspondingsignal SGD1 ₀) can be a selected select gate. Select gate 285 of theselected block (associated with signal SGD0 ₀) can be an unselectedselect gate. Select gate 280 of the selected block (associated withsignal SGS₀) can be a selected select gate. In memory block 203 ₁,control gates 250, 251, 252, and 253, (associated with signals WL0 ₁,WL1 ₁, WL2 ₁, and WL3 ₁) can be unselected control gates. Select gates280, 285, and 286 of an unselected block (associated with signals SGS₁,SGD0 ₁, and SGD1 ₁) can be unselected select gates.

As shown in FIG. 4, write stage 315 can be performed during a timeinterval between times Tb and Td to store information in the selectedmemory cell. Reset stage 316 can be performed during a time intervalbetween times Td and Te. Write verify stage 317 can be performed aftertime Te.

In write stage 315, memory device 200 can apply a voltage Vpassw tocontrol gate 251 of the selected block (associated with signal WL1 ₀)during a time interval between time Tb and Tc and a voltage Vprg (e.g.,a programming voltage) to control gate 251 of the selected block duringa time interval between times Tc and Td. The voltage on line 251 of theselected block can be at a voltage V0 between times Ta and Tb. VoltageV0 can have a value of zero volts (e.g., ground potential). Each ofvoltages Vpassw and Vprg can have a positive value greater than that ofvoltage V0. The value of voltage Vprg can be greater than the value ofvoltage Vpassw.

Memory device 200 can apply voltage Vpassw to control gates 250, 252,and 253 of the selected block (associated with signals WL0 ₀, WL2 ₀, andWL3 ₀) during a time interval between time Tb and Td. The voltage oncontrol gates 250, 252, and 253 of the selected block can be at voltageV0 between times Ta and Tb.

Memory device 200 can apply a voltage Vsg to select gate 286 of theselected block (associated with signals SGD1 ₀) during a time intervalbetween time Tb and Td. The voltage on select gate 286 of the selectedblock can be at voltage V0 between times Ta and Tb. Voltage Vsg can havea positive value.

Memory device 200 can apply voltage V0 to select gates 280 and 285 ofthe selected block (associated with signals SGS₀ and SGD0 ₀) during atime interval between time Ta and Td.

The voltage on lines 270, 271, and 272 (associated with signals BL0,BL1, and BL2 in FIG. 4) can be at voltage Vbl or voltage V0, dependingon the value of information to be stored in the selected memory cell.Memory device 200 can apply a voltage Vsrc to line 291 (associated withsignal SRC) during a time interval between time Tb and Td. Voltage Vsrccan have a positive value. For example, voltage Vsrc can have a valueequal to the supply voltage (e.g., Vcc) of memory device 200.

With respect to an unselected block, the waveform of signals WL0 ₁, WL1₁, WL2 ₁, WL3 ₁ are shown in dashed lines to indicate that correspondingcontrol gates 250, 251, 252, and 253 (of the unselected block) can be ina float condition (e.g., electrically unconnected to another element).Similarly, signals SGS₁, SGD0 ₁, and SGD1 ₁ are shown in dashed lines toindicate that corresponding select gates 280, 285, and 286 of theunselected block can be in a float condition.

In write stage 315, in selected memory block 203 ₀, the potentials ofbody 240 (FIG. 2B) of memory cell string 231 (selected) and unselectedmemory cell strings that share the same control gates 250, 251, 252, and253 with memory cell string 231 may fall to a negative potential (e.g.,−5 volts) at the end of write stage 315 (e.g., at time 398 in FIG. 4).The negative potential may cause undesirable situations in memory block203 ₀ and may affect other operations (e.g., write verify stage 317)performed on memory block 203 ₀. The undesirable situations may includea gate stress situation and a hot electron injection situation.

Gate stress situation may occur in a particular memory cell (e.g., oneof memory cells 210, 211, 212, and 213 in FIG. 2B) that has a relativelylow threshold voltage. The gate stress in a particular memory cell maycreate a favorable condition for excess electrons from body 240 (due tothe negative potential) to move (e.g., by tunneling) from body 240 tocharge storage material 204 (e.g., floating gate) of that particularmemory cell.

Hot electron injection situation may occur near both ends of body 240(e.g., ends close to memory cells 210 and 213 in FIG. 2B). The electricfield at these ends of body 240 may be relatively high. Excess electronsfrom body 240 (due to the negative potential) may leak from body 240 atthese ends and become hot electrons. In some cases, for example, incases where particular memory cells near these ends (e.g., memory cells210 and 213) have a relatively low threshold voltage, the hot electronsmay be injected into charge storage material 204 of these particularmemory cells.

The gate stress and hot electron injection situations, as describedabove, may alter (e.g., increase) the threshold voltage of one or moreof memory cells 210, 211, 212, and 213. Thus, the values of information(which can be based on the threshold voltage values) stored in memorycells 210, 211, 212, and 213 may deviate from their intended values. Asa result, errors in the information stored in memory cells 210, 211,212, and 213 may occur. Reset stage 316 (FIG. 3 and FIG. 4) may beperformed to control (e.g., increase) the potential of body 240 duringat least a portion of the reset stage 316. Reset stage 316 may resetbody 240 from a negative potential (e.g., −5V) to zero or near zerovolts by the end of reset stage 316. As a result, the mentioned gatestress situation and hot electron injection situations may be avoided.This may improve the reliability of memory device 200.

Reset stage 316 can include either the reset stage 516 (FIG. 5) or resetstage 616 (FIG. 6). Write verify stage 317 can include a read stage,such as read stage 1015 described below with reference to FIG. 10, FIG.11A, and FIG. 11B or read stage 1235 described below with reference toFIG. 12.

FIG. 5 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during a reset stage 516,according to an embodiment of the invention. Reset stage 516 cancorrespond to reset stage 316 of FIG. 4. Thus, the waveforms associatedwith reset stage 516 in FIG. 5 can be used for the reset stage 316 inFIG. 4.

As shown in FIG. 5, reset stage 516 can begin at time 598 and end attime T4. Time 598 can correspond to time 398 (the end of write stage315) in FIG. 4. The following description refers to FIG. 2A through FIG.5.

As described above, body 240 (FIG. 2B) can have a negative potential atthe end of write stage 315 (FIG. 3 and FIG. 4). A lack of holes in body240 can be one of the factors that may cause the negative potential tooccur. Memory device 200 can perform reset stage 516 to generategate-induced drain leakage (GIDL) current at one or both of junctions244 and 245 (FIG. 2B) of body 240. Holes can be generated by the GIDLcurrent. Memory device 200 can control the potential of body 240, suchas by injecting holes (generated from GIDL current) into body 240 inorder to increase the potential of body 240, thereby removing orminimizing the negative potential in body 240.

GIDL current can be induced in at junction 244 of body 240 (FIG. 2B)when the value of the voltage on line 270 is higher than the value ofthe voltage on select gate 286. GIDL current can be induced in atjunction 245 of body 240 when the value of the voltage on line 291 ishigher than the value of the voltage on select gate 280.

Thus, by applying appropriate voltages to lines 270, 271, 272, 291 andselect gates 280, 285, and 286, memory device 200 can induce GIDLcurrent in the body (e.g., body 240) of memory cell string 231(selected) and unselected memory cell strings in memory block 203 ₀(FIG. 2A).

For example, between times T1 and T2 in FIG. 5, memory device 200 canapply voltage V1 to lines 270, 271, and 272 (associated with signalsBL0, BL1, and BL2), voltage V2 to line 291 (associated with signal SRC),and voltage V0 to select gates 280, 285, and 286 of the selected block(associated with signals SGS₀, SGD0 ₀, and SGD1 ₀). At time T2, voltageV1 can be decreased such that it can reach voltage V0 by the end ofreset stage 516 (e.g., between times T3 and T4). Similarly, voltage V2can be decreased such that it can reach voltage V0 by the end of resetstage 516.

Each of voltages V1 and V2 can have a positive value and can be greaterthan the value of voltage V0. The values of voltages V1 and V2 can bethe same or different. For example, the value of voltage V1 can be equalto, less than, or greater than the value of voltage V2. With theseapplied voltages, GIDL current can be generated to provide holes to body240. Voltage V0 applied to select gates 280, 285, and 286 of theselected block between times T1 and T2 can be zero volts. Alternatively,a voltage having a positive value can be applied to select gates 280,285, and 286 of the selected block between times T1 and T2 as long assuch positive value is less than the value of voltage V1 and V2, so thatGIDL current can occur at junction 244 or 245 or both (FIG. 2B) toprovide holes to body 240 between times T1 and T2.

Thus, in reset stage 516, memory device 200 can increase the voltage onlines 270, 271, and 272 from voltage V0 (at time T0) to voltage V1, holdlines 270, 271, and 272 at voltage V1 and hold select gates 280, 285,and 286 of the selected block at voltage V0 for a time interval (e.g.,between times T1 and T2) to induce GIDL current (e.g., at junction 244in FIG. 2B). In a similar fashion, in reset stage 516, memory device 200can increase the voltage on line 291 from voltage V0 to voltage V2 andhold line 291 at voltage V2 for a time interval to induce GIDL current(e.g., at junction 245 in FIG. 2B).

Between times T0 and T4, control gates 250, 251, 252, and 253(associated with signals WL0 ₀, WL1 ₀, WL2 ₀, and WL3 ₀) in memory block203 ₀ can be applied with voltage V0. In memory block 203, control gates250, 251, 252, and 253 (associated with signals WL0 ₁, WL1 ₀, WL2 ₁, andWL3 ₁) and select gates 280, 285, and 286 (associated with signals SGS₁,SGD0 ₁, and SGD1 ₀) can be put in a float condition.

FIG. 5 shows an example where memory device 200 can increase the voltageon lines 270, 271, 272, (e.g., from voltage V0 to voltage V1) and alsoon line 291 (e.g., from voltage V0 to voltage V2). However, memorydevice 200 can be configured to increase either the voltage on line 291or the voltage on lines 270, 271, and 272. For example, between times T1and T2, memory device 200 can increase the voltage on lines 270, 271,and 272 (e.g., from voltage V0 to voltage V1) and hold line 291 at thesame voltage V0 from time T0 to time T2. In another example, memorydevice 200 can increase the voltage on line 291 (e.g., from voltage V0to voltage V2) and hold lines 270, 271, and 272 at the same voltage V0from time T0 to time T2.

FIG. 6 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during a reset stage 616 inwhich a voltage on at least one of the control gates has a positivevalue, according to an embodiment of the invention. Memory device 200can be configured to perform reset stage 616 as an alternative for resetstage 516 of FIG. 5. Reset stage 616 can correspond to reset stage 316of FIG. 4. Thus, the waveforms associated with reset stage 616 in FIG. 6can be used for the reset stage 316 in FIG. 4.

As shown in FIG. 6, reset stage 616 can begin at time 698 and end attime T7. Time 698 can correspond to time 398 (the end of write stage315) of FIG. 4. Similar to reset stage 516 of FIG. 5, memory device 200can perform reset stage 616 to induce GIDL current at one or both ofjunctions 244 and 245 (FIG. 2B) of body 240 to control the potential ofbody 240, such as by injecting holes (generated from GIDL current) intobody 240 in order to increase the potential of body 240, therebyremoving or minimizing the negative potential in body 240.

In reset stage 616, however, memory device 200 can apply a voltage V3having a positive value to control gates 250, 251, 252, and 253 of theselected block (associated with signals WL0 ₀, WL1 ₀, WL2 ₀, and WL3 ₀)for at least a portion of time interval between times T0 and T7. Forexample, memory device 200 can apply voltage V3 to control gates 250,251, 252, and 253 of the selected block between times T3 and T4 while itapplies voltage V5 to lines 270, 271, and 272 (associated with signalsBL0. BL1, and BL2) and voltage V6 to line 291 (associated with signalSRC). Applying the voltages (e.g., V3, V5, and V6) this way may reducethe voltage difference and the electric field at regions between body240 and lines 270, 271, 272, and 291 (FIG. 2B).

Between times T0 and T3 in FIG. 6, select gates 280, 285, and 286 of theselected block (associated with signals SGS₀, SGD0 ₀, and SGD1 ₀) can beapplied with a voltage V4 (having a positive value). At time T2, voltageV4 can be decreased such that it can reach voltage V0 by time T3 andremain at voltage V0 from time T3 to time T7.

At time T4, voltage V3 on control gates 250, 251, 252, and 253 of theselected block can be decreased such that it can reach voltage V0 bytime T5 and remain at voltage V5 from time T5 to time T7.

At time T5, voltage V5 on lines 270, 271, and 272 can be decreased suchthat it can reach voltage V0 by the end of reset stage 616 (e.g.,between times T6 and T7). Similarly, at time T5, voltage V6 on line 291can be decreased such that it can reach voltage V0 by the end of resetstage 616.

The values of voltages V5 and V6 can be the same or different. Forexample, the value of voltage V5 can be equal to, less than, or greaterthan the value of voltage V6. Voltage V0 applied to select gates 280,285, and 286 of the selected block between times T3 and T5 can be zerovolts. Alternatively, a voltage having a positive value can be appliedto select gates 280, 285, and 286 of the selected block between times T3and T5 as long as such positive value is less than the value of voltageV5 and V6, so that GIDL current can occur at junction 244 or 245 or both(FIG. 2B) to provide holes to body 240 between times T3 and T5.

Thus, in reset stage 616, memory device 200 can increase the voltage onlines 270, 271, and 272 from voltage V0 (at time T0) to voltage V5, holdlines 270, 271, and 272 at voltage V5 and hold select gates 280, 285,and 286 of the selected block at voltage V0 for a time interval (e.g.,between times T3 and T5) to induce GIDL current (e.g., at junction 244in FIG. 2B). In a similar fashion, in reset stage 616, memory device 200can increase the voltage on line 291 from voltage V0 to voltage V6 andhold line 291 at voltage V6 for a time interval to induce GIDL current(e.g., at junction 245 in FIG. 2B).

FIG. 6 shows an example where memory device 200 can increase the voltageon lines 270, 271, 272 and 291 (e.g., from voltage V0 to voltage V5 orV6). However, memory device 200 can increase the voltage on only line291 or the voltage on only lines 270, 271, and 272. For example, betweentimes T3 and T5, memory device 200 can increase the voltage on onlylines 270, 271, and 272 (e.g., from voltage V0 to voltage V5) and holdline 291 at the same voltage V0 from time T0 to time T7. In anotherexample, memory device 200 can increase the voltage on only line 291(e.g., from voltage V0 to voltage V6) and hold lines 270, 271, and 272at the same voltage V0 from time T0 to time T7.

FIG. 7 shows a diagram illustrating a write operation 710 of memorydevice 200 of FIG. 2A and FIG. 2B, according to an embodiment of theinvention. Memory device 200 can be configured to perform writeoperation 710 as an alternative for write operation 310 (FIG. 3 and FIG.4). In FIG. 7, write operation 710 can include stages (e.g., 315, 316,and 317) similar to or identical to those of write operation 310 (FIG.3). For simplicity, description of similar or identical elements betweenwrite operations 310 and 710 is not repeated in the description of FIG.7.

As shown in FIG. 7, reset stage 316 can be performed immediately beforeand/or after write stage 315. For example, before time 791 at thebeginning of write stage 315, a reset stage 316 can be performed. Then,another reset stage 316 can be performed at the end of write stage 315(e.g., at time 398). In some cases in memory device 200, body 240 (FIG.2B) may have negative potential before time 791 (e.g., before writestage 315 is performed). Performing reset stage 316 before time 791 mayremove excess electrons from body 240 in order to increase the potentialof body 240 (e.g., increase from a negative potential to about zerovolts). This could improve the operation of write stage 315, such as byavoiding voltage boosting failure that may occur in body 240 duringwrite stage 315.

FIG. 8 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during write operation 710 ofFIG. 7, according to an embodiment of the invention. The waveforms inFIG. 8 can be similar to or identical to those in FIG. 4, except for thewaveforms associated with reset stage 316 (between times Ta and Tb)performed before write stage 315 is performed (e.g., before time 791).As shown in FIG. 8, the waveforms associated with reset stage 316between times Ta and Tb can be similar or identical to those shown inFIG. 5 or FIG. 6.

FIG. 9 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during a write operation 910,according to an embodiment of the invention. Memory device 200 can beconfigured to perform write operation 910 (FIG. 9) as an alternative forwrite operation 310 (FIG. 3 and FIG. 4) or write operation 710 (FIG. 7and FIG. 8).

In FIG. 9, write stage 925 can store information in a selected memorycell among memory cells 210, 211, 212, and 213 of a memory cell string,such as memory cell string 231. Write verify stage 927 can determinewhether the value of information stored in the selected memory cell(stored by write stage 925) reaches a target value. Reset stage 926 canbe performed to control the potential of body 240, such as by injectingholes (e.g., generated by GIDL current) into body 240 in order toincrease the potential of body 240, thereby removing or minimizing thenegative potential in body 240 present at the end of write stage 925.

In write stage 925, memory device 200 can apply voltage Vprg to controlgate 251 of the selected block (associated with signal WL₁₀) betweentimes Ta and Tc, voltage Vpassw to control gates 250, 252, and 253 ofthe selected block (associated with signals WL₀₀, WL₂₀, and WL₃₀)between time Ta and Tf, and voltage Vsg to select gate 286 of theselected block between times Ta and Tb. Memory device 200 can applyvoltage V0 to select gates 280 and 285 of the selected block (associatedwith signals SGS₀ and SGD0 ₀) between times Ta and Tj.

At time Tc, voltage Vprg can be decreased such that it can reach voltageV7 by time Td. Voltage V7 can have a positive value. At time Tb, voltageVsg can be decreased such that it can reach voltage V0 by time Tc andremain at voltage V0 from time Tc to time Tj.

In write stage 925, the voltage on lines 270, 271, and 272 (associatedwith signals BL0, BL1, and BL2) can be at voltage Vbl or voltage V0,depending on the value of information to be stored in the selectedmemory cell. Memory device 200 can apply a voltage Vsrc to line 291(associated with signals SRC) during a time interval between time Ta andTd.

Control gates 250, 251, 252, and 253 (associated with signals WL0 ₁. WL1₁, WL2 ₁, and WL3 ₁) and select gates 280, 285, and 286 (associated withsignals SGS₁, SGD0 ₁, and SGD1 ₁) of the unselected block can be put ina float condition.

At the end of write stage 925 (e.g., at time 998), the potentials ofbody 240 (FIG. 2B) of memory cell string 231 (selected) and unselectedmemory cell strings that share the same control gates 250, 251, 252, and253 with memory cell string 231 may fall to a negative potential. Resetstage 926 can be performed to inject holes (e.g., generated by GIDLcurrent) into body 240.

In reset stage 926, memory device 200 can hold the voltage on controlgate 251 of the selected block at V7 from time Td to time Te and holdthe voltage on control gates 250, 252, and 253 of the selected block atVpassw from time Td to time Tf. At time Te, voltage Vprg on control gate251 of the selected block can be decreased such that it can reachvoltage V8 by time Tg. The voltage on control gate 251 of the selectedblock can remain at voltage V8 through the end of reset stage (e.g.,between times Ti and Tj). At time Tf, voltage Vpassw on control gates250, 252, and 253 of the selected block can be decreased such that itcan reach voltage V9 by time Tg. The voltage on control gates 250, 252,and 253 can remain at voltage V9 through the end of reset stage 926(e.g., between times Ti and Tj).

Each of voltages V8 and V9 can have a positive value. The values ofvoltages V8 and V9 can be the same or different. For example, the valueof voltage V8 can be equal to, less than, or greater than the value ofvoltage V9. Alternatively, one or both of voltages V8 and V9 can be zerovolts. However, using voltages V8 and V9 with positive values may reducepower consumed by memory device 200 when it performs write verify stage927 after reset stage 926.

In reset stage 926, memory device 200 can increase the voltage on lines270, 271, and 272 from voltage V0 (at time Td) to voltage V10 and holdlines 270, 271, and 272 at voltage V10 for a time interval (e.g.,between times Td and Th) to induce GIDL current (e.g., at junction 244in FIG. 2B). At time Th, voltage V10 can be decreased such that it canreach voltage V0 by the end of reset stage 926 (e.g., between times Tiand Tj). In a similar fashion, in reset stage 926, memory device 200 canincrease the voltage on line 291 from voltage V0 to voltage V11 and holdline 291 at voltage V11 for a time interval to induce GIDL current(e.g., at junction 245 in FIG. 2B). Then, voltage V11 can be decreasedsuch that it can reach voltage V0 by the end of reset stage 926.

Each of voltages V10 and V11 can have a positive value. The values ofvoltages V10 and V11 can be the same or different. For example, thevalue of voltage V10 can be equal to, less than, or greater than thevalue of voltage V11. Voltage V0 applied to select gates 280, 285, and286 of the selected block between times Td and Th can be zero volts.Alternatively, a voltage having a positive value can be applied toselect gates 280, 285, and 286 of the selected block between times Tdand Th as long as such positive value is less than the value of voltageV10 and V11, so that GIDL current can occur at junction 244 or 245 orboth (FIG. 2B) to provide holes to body 240 between times Td and Th.

FIG. 10 shows a diagram illustrating a read stage 1015 and a reset stage1016 of a read operation 1010 of memory device 200 of FIG. 2A and FIG.2B, according to an embodiment of the invention. The followingdescription refers to FIG. 2A, FIG. 2B, and FIG. 10. In read stage 1015,memory device 200 (FIG. 2A) can determine (e.g., read) the value ofinformation stored in a selected memory cell among memory cells 210,211, 212, and 213 of a memory cell string, such as memory cell string231. Reset stage 1016 can be performed at the end of read stage 1015(e.g., at time 1097). As shown in FIG. 10, memory device 200 can beconfigured to perform reset stage 1016 when signal RESET has levelV_(ENABLE). Memory device 200 can be configured to bypass reset stage1016 in read operation 1010. However, as described in more detail belowwith reference to FIG. 11A and FIG. 11B, including reset stage 1016 inread operation 1010 (FIG. 3) may improve the reliability memory device200.

FIG. 11A is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during read operation 1010 ofFIG. 10, according to an embodiment of the invention. In FIG. 11A,stages 1015 and 1016 correspond to those shown in FIG. 10. The signals(e.g., WL0 ₁, WL1 ₁. WL2 ₁, and WL3 ₁) in FIG. 11A correspond to thesame signals shown in FIG. 2A. The following description refers to FIG.2A. FIG. 2B, FIG. 10, and FIG. 11A.

Selected and unselected elements during read operation 1010 can be thesame as those in write operation 310 (FIG. 3 and FIG. 4). For example,in read operation 1010, memory block 203 ₀ (FIG. 2A) is assumed to be aselected memory block, memory block 203 ₁ is assumed to be an unselectedmemory block, memory cell string 231 is assumed to be a selected memorycell string. Memory cell string 231 and memory cell 211 of memory cellstring are assumed to be a selected memory cell string and a selectedmemory cell, respectively. Thus, control gate 251 of the selected block(associated with signal WL1 ₀) can be a selected control gate. Controlgates 250, 252, and 253 of the selected block (associated with signalsWL0 ₀, WL2 ₀, and WL3 ₀) can be unselected control gates. Select gate286 of the selected block (associated with corresponding signal SGD1 ₀)can be a selected select gate. Select gate 285 of the selected block(associated with signal SGD0 ₀) can be an unselected select gate. Selectgate 280 of the selected block (associated with signal SGS₀) can be aselected select gate. In memory block 203 ₁, control gates 250, 251,252, and 253, (associated with signals WL0 ₁, WL1 ₁, WL2 ₁, and WL3 ₁)can be unselected control gates. Select gates 280, 285, and 286 of theunselected block (associated with signals SGS₁, SGD0 ₁, and SGD1 ₁) canbe unselected select gates.

As shown in FIG. 11A, read stage 1015 can be performed during a timeinterval between times Ti and Tm to determine the value of informationstored in the selected memory cell. Reset stage 1016 can be performedduring a time interval between times Tm and Tn.

In read stage 1015, memory device 200 can apply a voltage Vread tocontrol gate 251 of the selected block (associated with signal WL1 ₀)during a time interval between times Tl and Tm. The voltage on line 251can be at voltage V0 before time Tl. Memory device 200 can apply avoltage Vpassr to control gates 250, 252, and 253 of the selected block(associated with signals WL0 ₀, WL2 ₀, and WL3 ₀) during a time intervalbetween time Tl and Tm. The voltage on control gates 250, 252, and 253can be at voltage V0 before time Tl. Each of voltages Vread and Vpassrcan have a positive value greater than that of voltage V0. The value ofvoltage Vpassr can be greater than the value of voltage Vread.

In read stage 1015, memory device 200 can apply a voltage Vsg to selectgate 286 of the selected block (associated with signals SGD1 ₀) andselect gate 280 of the selected block (associated with signals SGS₀).The voltage on select gates 280 and 286 can be at voltage V0 beforetimes Tl. Memory device 200 can apply voltage V0 to select gate 285 ofthe selected block (associated with signal SGD0 ₀) in read stage 1015.

The voltage on lines 270, 271, and 272 (associated with signals BL0,BL1, and BL2) in read stage 1015 can be at voltage Vblr or voltage V0,depending on the value of information stored in the selected memorycell. The voltage on line 291 (associated with signal SRC) in read stage1015 can be at voltage V0.

Control gates 250, 251, 252, and 253 of the unselected block (associatedwith signals WL0 ₁, WL1 ₁, WL2 ₁, and WL3 ₁) and select gates 280, 285,and 286 of the unselected block (associated with signals SGS₁, SGD0 ₁,and SGD1 ₁) can be in a float condition.

In read stage 1015, in memory block 203 ₀, the potentials of body 240(FIG. 2B) of memory cell string 231 (selected) and unselected memorycell strings that share the same control gates 250, 251, 252, and 253with memory cell string 231 may fall to a negative potential at the endof read stage 1015 (e.g., at time 1097). The negative potential maycause undesirable situations in memory block 203 ₀, such as gate stressand hot electron injection situations, as described above (e.g., withreference to FIG. 4 through FIG. 6). Reset stage 1016 (FIG. 10 and FIG.11A) may be performed to control (e.g., increase) the potential of body240, such as to increase the potential of body 240 from a negativepotential to zero or near zero volts. As a result, the gate stresssituation and hot electron injection situations in read stage 1015 maybe avoided. Reset stage 1016 can include either the reset stage 516 orreset stage 616 described above with reference to FIG. 5 and FIG. 6,respectively. Thus, the waveforms associated with reset stage 516 inFIG. 5 or reset stage 616 in FIG. 6 can be used for the reset stage 1016in FIG. 11A.

As mentioned above in the description of FIG. 3, write verify stage 317can include a read stage, such as read stage 1015 (FIG. 10 and FIG.11A). Thus, the waveforms for the combination of write verify stage 317and reset stage 316 in FIG. 3 (reset stage 316 after time 399 in FIG. 3)can be similar to or identical to those of the combination of read stage1015 and reset stage 1016 of FIG. 11A.

FIG. 11B is an alternative timing diagram showing waveforms of some ofthe signals of the memory device of FIG. 2A and FIG. 2B during the readoperation of FIG. 10, according to an embodiment of the invention. InFIG. 11B, stages 1015 and 1016 correspond to those shown in FIG. 10. Thesignals (e.g., WL0 ₁, WL1 ₁, WL2 ₁, and WL3 ₁) in FIG. 11B correspond tothe same signals shown in FIG. 2A. The following description refers toFIG. 2A, FIG. 2B, FIG. 10, and FIG. 11B.

Selected and unselected elements during read operation 1010 can be thesame as those in write operation 310 (FIG. 3 and FIG. 4). For example,in read operation 1010, memory block 203 ₀ (FIG. 2A) is assumed to be aselected memory block, memory block 203 ₁ is assumed to be an unselectedmemory block, memory cell string 231 is assumed to be a selected memorycell string. Memory cell string 231 and memory cell 211 of memory cellstring are assumed to be a selected memory cell string and a selectedmemory cell, respectively. Thus, control gate 251 of the selected block(associated with signal WL1 ₀) can be a selected control gate. Controlgates 250, 252, and 253 of the selected block (associated with signalsWL0 ₀, WL2 ₀, and WL3 ₀) can be unselected control gates. Select gate286 of the selected block (associated with corresponding signal SGD1 ₀)can be a selected select gate. Select gate 285 of the selected block(associated with signal SGD0 ₀) can be an unselected select gate. Selectgate 280 of the selected block (associated with signal SGS₀) can be aselected select gate. In memory block 203 ₁, control gates 250, 251,252, and 253, (associated with signals WL0, WL1 ₁, WL2 ₁, and WL3 ₁) canbe unselected control gates. Select gates 280, 285, and 286 of theunselected block (associated with signals SGS₁, SGD0 ₁, and SGD1 ₁) canbe unselected select gates.

As shown in FIG. 11B, read stage 1015 can be performed during a timeinterval between times Tl and Tm to determine the value of informationstored in the selected memory cell. Reset stage 1016 can be performedduring a time interval between times Tm and Tn.

In read stage 1015, memory device 200 can apply voltages havingdifferent values to control gate 251 of the selected block (associatedwith signal WL1 ₀) during different time intervals between times Tl andTm. For example, memory device 200 can apply voltages Vpre+Vc. Vread,and Vpre+Vc to control gate 251 of the selected block in the order shownin FIG. 11B. The voltage on line 251 can be at voltage V0 before timeTl. Voltage Vpre can have a value equal to the supply voltage (e.g.,Vcc) of memory device 200. Voltage Vc can have a positive value. VoltageVread can have a positive value greater than that of voltage V0 and lessthan the sum of voltage Vpre+Vc.

Memory device 200 can apply voltages having different values to controlgates 250, 252, and 253 of the selected block (associated with signalsWL0 ₀, WL2 ₀, and WL3 ₀) during different time intervals between timesTi and Tm. For example, memory device 200 can apply voltages Vpre+Vc,Vpassr, and Vpre+Vc to control gates 250, 252, and 253 of the selectedblock the order shown in FIG. 11B. The voltage on control gates 250,252, and 253 can be at voltage V0 before time Tl. Voltage Vpassr canhave a positive value greater than that of voltage V0 and greater thanthe sum of voltage Vpre+Vc.

In read stage 1015, memory device 200 can apply different voltages toselect gate 286 of the selected block (associated with signals SGD1 ₀)during different time intervals between times Tl and Tm. As shown inFIG. 11B, the voltages applied to select gate 286 of the selected blockcan be the same as the voltages (e.g., Vpre+Vc, Vpassr, and Vpre+Vc)applied to control gates 250, 252, and 253 of the selected block(associated with signals WL0 ₀, WL2 ₀, and WL3 ₀).

Memory device 200 can apply voltage Vpassr to select gate 280 of theselected block (associated with signals SGS₀) during a time intervalbetween times Tl and Tm. For example, as shown in FIG. 11B, voltageVpassr can be applied to select gate 280 of the selected block whilevoltage Vpassr is also applied to control gates 250, 252, and 253 of theselected block (associated with signals WL0 ₀, WL2 ₀, and WL3 ₀) and toselect gate 286 of the selected block (associated with signals SGD1 ₀).The voltage on select gate 280 of the selected block can be at voltageV0 before time Tl.

Memory device 200 can apply voltage Vpre+Vc to select gate 285 of theselected block (associated with signal SGD0 ₀) during different timeintervals between times Tl and Tm. For example, as shown in FIG. 11B,voltage Vpre+Vc can be applied to gate 285 of the selected block whilevoltage Vpre+Vc is also applied to control gate 251 of the selectedblock (associated with signal WL1 ₀), to control gates 250, 252, and 253of the selected block (associated with signals WL0 ₀, WL2 ₀, and WL3 ₀),and to select gate 286 of the selected block (associated with signalsSGD1 ₀). The voltage on select gate 285 of the selected block can be atvoltage V0 before time Tl.

The voltage on lines 270, 271, and 272 (associated with signals BL0.BL1, and BL2) in read stage 1015 can be at voltage Vpre or voltage Vblr(e.g., V0) depending on the value of information stored in the selectedmemory cell. The voltage on line 291 (associated with signal SRC) inread stage 1015 can be at voltage V0.

Control gates 250, 251, 252, and 253 of the unselected block (associatedwith signals WL0 ₁, WL1 ₁, WL2 ₁, and WL3 ₁) and select gates 280, 285,and 286 of the unselected block (associated with signals SGS₁, SGD0 ₁,and SGD1 ₁) can be in a float condition.

In read stage 1015, in memory block 203 ₀, the potentials of body 240(FIG. 2B) of memory cell string 231 (selected) and unselected memorycell strings that share the same control gates 250, 251, 252, and 253with memory cell string 231 may fall to a negative potential at the endof read stage 1015 (e.g., at time 1097). The negative potential maycause undesirable situations in memory block 203 ₀, such as gate stressand hot electron injection situations, as described above (e.g., withreference to FIG. 4 through FIG. 6). Reset stage 1016 (FIG. 10 and FIG.11B) may be performed to control (e.g., increase) the potential of body240, such as to increase the potential of body 240 from a negativepotential to zero or near zero volts. As a result, the gate stresssituation and hot electron injection situations in read stage 1015 maybe avoided. Reset stage 1016 can include either the reset stage 516 orreset stage 616 described above with reference to FIG. 5 and FIG. 6,respectively. Thus, the waveforms associated with reset stage 516 inFIG. 5 or reset stage 616 in FIG. 6 can be used for the reset stage 1016in FIG. 11B.

As mentioned above in the description of FIG. 3, write verify stage 317can include a read stage, such as read stage 1015 (FIG. 10 and FIG.11B). Thus, the waveforms for the combination of write verify stage 317and reset stage 316 in FIG. 3 (reset stage 316 after time 399 in FIG. 3)can be similar to or identical to those of the combination of read stage1015 and reset stage 1016 of FIG. 11B.

FIG. 12 is a timing diagram showing waveforms of some of the signals ofmemory device 200 of FIG. 2A and FIG. 2B during a read operation 1230,according to an embodiment of the invention. Memory device 200 can beconfigured to perform read operation 1230 (FIG. 12) as an alternativefor read operation 1010 (FIG. 10 and either FIG. 11A or FIG. 11B).

In FIG. 12, read stage 1235 can determine the value of informationstored in a selected memory cell among memory cells 210, 211, 212, and213 of a memory cell string, such as memory cell string 231. Reset stage1236 can be performed to control the potential of body 240, such as byinjecting holes (e.g., generated by GIDL current) into body 240 in orderto remove or minimize the negative potential in body 240, as describedabove with reference to FIG. 4 through FIG. 6.

In read stage 1235, memory device 200 can apply voltage Vread to controlgate 251 of the selected block (associated with signal WL1 ₀) betweentimes Tp and Tu, voltage Vpassr to control gates 250, 252, and 253 ofthe selected block (associated with signals WL0 ₀, WL2 ₀, and WL3 ₀)between time Tp and Tt, and voltage Vsg to select gates 286 and 280 ofthe selected block (associated with signals SGD1 ₀ and SGS₀) betweentimes Tp and Tq. Memory device 200 can apply voltage V0 to select gate285 of the selected block (associated with signals SGD0 ₀) between timesTp and Tx. At time Tq, voltage Vsg can be decreased such that it canreach voltage V0 at time Tr.

The voltage on lines 270, 271, and 272 (associated with signals BL0,BL1, and BL2) in read stage 1235 can be at voltage Vblr or voltage V0,depending on the value of information stored in the selected memorycell. The voltage on line 291 in read stage 1235 can be at voltage V0.

Control gates 250, 251, 252, and 253 of an unselected block (associatedwith signals WL0 ₁, WL1 ₁, WL2 ₁, and WL3 ₁) and select gates 280, 285,and 286 of an unselected block (associated with signals SGS₁, SGD0 ₁,and SGD1 ₁) can be in a float condition.

At the end of read stage 1235 (e.g., at time 1299), the potentials ofbody 240 (FIG. 2B) of memory cell string 231 (selected) and unselectedmemory cell strings that share the same control gates 250, 251, 252, and253 with memory cell string 231 may fall to a negative potential. Resetstage 1236 can be performed to control the potential of body 240, suchas by injecting holes (e.g., generated by GIDL current) into body 240 inorder to remove or minimize the negative potential in body 240.

In reset stage 1236, memory device 200 can hold the voltage on controlgate 251 of the selected block at Vread from time Ts to time Tu and holdthe voltage on control gates 250, 252, and 253 of the selected block atVpassr from time Ts to time Tt. At time Tt, voltage Vpassr can bereduced such that it can reach voltage V0 by time Tu. At time Tu,voltage Vread can be reduced such that it can reach voltage V0 by timeTv.

In reset stage 1236, memory device 200 can increase the voltage on lines270, 271, and 272 from voltage V0 (at time Ts) to voltage V12 and holdlines 270, 271, and 272 at voltage V12 for a time interval (e.g.,between times Ts and Tv) to induce GIDL current (e.g., at junction 244in FIG. 2B). At time Tv, voltage V12 can be decreased such that it canreach voltage V0 by the end of reset stage 1236 (e.g., between times Twand Tx). In a similar fashion, in reset stage 1236, memory device 200can increase the voltage on line 291 from voltage V0 to voltage V13,hold line 291 at voltage V13 for a time interval to induce GIDL current(e.g., at junction 245 in FIG. 2B). Then, voltage V13 can be decreasedsuch that it can reach voltage V0 by the end of reset stage 1236.

Each of voltages V12 and V13 can have a positive value. The values ofvoltages V12 and V9 can be the same or different. For example, the valueof voltage V12 can be equal to, less than, or greater than the value ofvoltage V9. Voltage V0 applied to select gates 280, 285, and 286 of theselected block between times Ts and Tv can be zero volts. Alternatively,a voltage having a positive value can be applied to select gates 280,285, and 286 between times Ts and Tv as long as such positive value isless than the value of voltage V12 and V13, so that GIDL current canoccur at junction 244 or 245 or both (FIG. 2B) to provide holes to body240 between times Ts and Tv.

As mentioned above in the description of FIG. 3, write verify stage 317can include a read stage, such as read stage 1235 of FIG. 12. Thus, thewaveforms for the combination of write verify stage 317 and reset stage316 of FIG. 3 (reset stage 316 after time 399 of FIG. 3) can be similarto or identical to the waveforms of the combination of read stage 1235and reset stage 1236 of FIG. 12.

FIG. 13 shows a diagram illustrating an erase verify stage 1315 and areset stage 1316 of an erase operation 1310 of memory device 200 of FIG.2A and FIG. 2B, according to an embodiment of the invention. Eraseverify stage 1315 and a reset stage 1316 can be performed after an erasestage (not shown) of erase operation 1310. In the erase stage,information from some or all memory cells (e.g., 210, 211, 212, and 213)in a memory block (e.g., 203 ₀ or 203 ₁ in FIG. 2A) can be erased.

In erase verify stage 1315 in FIG. 13, memory device 200 can determinewhether the state of selected memory cells in a particular memory blockreach their target states after an erase stage is performed. Eraseverify stage 1315 can include a read stage, such as read stage 1015 ofFIG. 10 and FIG. 11A or read stage 1015 of FIG. 10 and FIG. 11B. Thus,operations and waveforms of signals associated with erase verify stage1315 (FIG. 13) can be similar to or identical to those of read stage1015.

As shown in FIG. 13, reset stage 1316 can be performed when signal RESEThas level V_(ENABLE) and can be performed at the end of erase verifystage 1315 (e.g., at time 1396). Reset stage 1315 can include resetstage 1016 of FIG. 10 and FIG. 11A or FIG. 10 and FIG. 11B. Thus,operations and waveforms of signals associated with reset stage 1316 canbe similar to or identical to those of reset stage 1016. Memory device200 can be configured to bypass reset stage 1316 in erase operation1310. However, performing reset stage 1316 in erase operation 1310 cancontrol the potential of body 240 at the end of erase verify stage, suchas by injecting holes (generated from GIDL current) into body 240 inorder to remove or minimize the negative potential in body 240 that mayotherwise be present in the body 240 at the end of the erase stage.

FIG. 14 is a flowchart for a method 1400 of performing an operation(e.g., read, write, or erase) in a device, according to an embodiment ofthe invention. Method 1400 can be used in a memory device such as memorydevice 100 (FIG. 1) and memory device 200 (FIG. 2A and FIG. 2B).

As shown in FIG. 14, activity 1410 of method 1400 can include receivinga command to perform an operation in a device. The command can include aread, write, or erase command. The command can be provided to the deviceby a memory controller or a processor external to the device.

Activity 1420 of method 1400 can include performing the operation basedon the command received in activity 1410. For example, the operationperformed in activity 1420 can include a write operation if the commandreceived in activity 1410 includes a write command. The write operationin activity 1420 can include a write operation described above, such aswrite operation 310 (FIG. 3 and FIG. 4), write operation 710 (FIG. 7 andFIG. 8), or write operation 920 (FIG. 9).

In another example, the operation performed in activity 1420 can includea read operation if the command received in activity 1410 includes aread command. The read operation in activity 1420 can include a readoperation described above, such as read operation 1010 (FIG. 10 andeither FIG. 11A or FIG. 11B) or read operation 1230 (FIG. 12).

In a further example, the operation performed in activity 1420 caninclude an erase operation if the command received in activity 1410includes an erase command. The erase operation in activity 1420 caninclude an erase operation described above, such as erase operation 1310(FIG. 13).

Activity 1430 of method 1400 can include controlling a potential of abody associated with a memory cell string of the device. The body inactivity 1430 can include a body of a memory cell string of the device,such as body 240 (FIG. 2B) of memory cell string 231 in FIG. 2A or othermemory cell string of memory device 200. Controlling the potential ofthe body in activity 1430 can include performing a reset stage, such asperforming one of the reset stages described above with reference toFIG. 1 through FIG. 13. Thus, controlling the potential of the body inactivity 1430 can include performing activities in a reset stagedescribed above with reference to FIG. 1 through FIG. 13. Suchactivities can include inducing GIDL current in a body associated with amemory cell string, injecting holes into a body associated with a memorycell string, removing excess electrons from a body associated with amemory cell string, increasing the potential of a body associated with amemory cell string, and other activities described above with referenceto FIG. 1 through FIG. 13.

As shown in FIG. 14, method 1400 can also include activity 1415, whichcan be similar to or identical to activity 1430. For example, activity1415 can include controlling a potential of a body associated with amemory cell string of the device. Controlling the potential of the bodyin activity 1415 can include performing activities in a reset stagedescribed above with reference to FIG. 1 through FIG. 13.

Activity 1415 can be performed before activity 1420 is performed. Forexample, if the command received in activity 1410 includes a writecommand, then, as described above, activity 1420 can perform a writeoperation, which can include a write stage. However, before the writestage in activity 1420 is performed, activity 1425 can be performed. Forexample, activity 1415 can include performing a reset stage before thewrite stage is performed in activity 1420. In some cases, method 1400may omits activity 1415.

The illustrations of apparatuses (e.g., memory devices 100 and 200) andmethods (e.g., operating methods associated with memory devices 100 and200, and methods associated with FIG. 14) are intended to provide ageneral understanding of the structure of various embodiments and arenot intended to provide a complete description of all the elements andfeatures of apparatuses that might make use of the structures describedherein. An apparatus herein can refer to, for example, circuitry, a die,a device (e.g., memory devices 100 and 200) or a system (e.g., acomputer, a cellular phone, or other electronic system) that includes adevice such as memory devices 100 and 200.

The apparatuses (e.g., memory devices 100 and 200 or part of memorydevices 100 and 200, including memory control unit 116 in FIG. 1, resetcircuit 195 in FIG. 1, and reset circuit 295 in FIG. 2A) described abovemay all be characterized as “modules” (or “module”) herein. Such modulesmay include hardware circuitry, single and/or multi-processor circuits,memory circuits, software program modules and objects and/or firmware,and combinations thereof, as desired and/or as appropriate forparticular implementations of various embodiments.

Memory devices 100 and 200 may be included in apparatuses (e.g.,electronic circuitry) such as high-speed computers, communication andsignal processing circuitry, single or multi-processor modules, singleor multiple embedded processors, multi-core processors, messageinformation switches, and application-specific modules includingmultilayer, multi-chip modules. Such apparatuses may further be includedas sub-components within a variety of other apparatuses (e.g.,electronic systems), such as televisions, cellular telephones, personalcomputers (e.g., laptop computers, desktop computers, handheldcomputers, tablet computers, etc.), workstations, radios, video players,audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3)players), vehicles, medical devices (e.g., heart monitor, blood pressuremonitor, etc.), set top boxes, and others.

The embodiments described above with reference to FIG. 1 through FIG. 14include apparatuses and methods having a memory cell string includingmemory cells located in different levels of the apparatus and a dataline coupled to the memory cell string. The memory cell string includesa pillar body associated with the memory cells. At least one of suchapparatus can include a module configured to store information in amemory cell among memory cells and/or to determine a value ofinformation stored in a memory cell among memory cells. The module canalso be configured to apply a voltage having a positive value to thedata line and/or a source to control a potential of the body. Otherembodiments including additional apparatuses and methods are described.

The above description and the drawings illustrate some embodiments ofthe invention to enable those skilled in the art to practice theembodiments of the invention. Other embodiments may incorporatestructural logical, electrical, process, and other changes. Examplesmerely typify possible variations. Portions and features of someembodiments may be included in, or substituted for, those of others.Many other embodiments will be apparent to those of skill in the artupon reading and understanding the above description.

1. An apparatus comprising: a memory cell string including memory cellscoupled between a first select transistor and a second selecttransistor, and a body associated with the memory cells and the firstand second select transistors, the memory cells and the first and secondtransistors located in different levels of the apparatus; a control gateassociated with a memory cell of the memory cells of the memory cellstring; a first select gate associated with the first select transistor;a second select gate associated with the second select transistor; adata line coupled to the body of memory cell string; a source coupled tothe body of memory cell string; and a memory control unit includinghardware circuitry, the memory control unit configured to: apply aground potential to the first and second select gates during at least aportion of an operation performed on the memory cell; apply a firstvoltage having a first value to the control gate in a first stage of theoperation, the first value being a positive value; apply a secondvoltage having a second value to the control gate in at least a portionof a second stage of the operation, the second value being less than thefirst value; and while the ground potential is applied to the first andsecond select gates in the second stage, perform at least one of, applya third voltage having a positive value to the data line, and apply afourth voltage having a positive value to the source.
 2. The apparatusof claim 1, wherein the third and fourth voltages have a same value. 3.The apparatus of claim 1, wherein the third and fourth voltages havedifferent values.
 4. The apparatus of claim 1, wherein the secondvoltage is the ground potential.
 5. The apparatus of claim 4, whereinthe memory control unit is configured to perform at least one of applythe third voltage to the data line and apply the fourth voltage to thesource while the second voltage is at the ground potential.
 6. Theapparatus of claim 1, wherein the operation includes a write operation.7. The apparatus of claim 1, wherein the operation includes a readoperation.
 8. The apparatus of claim 1, wherein the operation includesan erase operation.
 9. An apparatus comprising: a memory cell stringincluding memory cells coupled between a first select transistor and asecond select transistor, and a body associated with the memory cellsand the first and second select transistors, the memory cells and thefirst and second transistors located in different levels of theapparatus; a control gate associated with a memory cell of the memorycells of the memory cell string; a first select gate associated with thefirst select transistor; a second select gate associated with the secondselect transistor; a data line coupled to the body of memory cellstring; a source coupled to the body of memory cell string; and a memorycontrol unit including hardware circuitry, the memory control unitconfigured to: apply a first voltage to the control gate in a firststage of an operation performed on the memory cell, the first voltagehaving a positive value; decrease the positive value of first voltage ina second stage of the operation; apply a ground potential to the firstand second select gates in the second stage; and while the groundpotential is applied to the first and second select gates in the secondstage, perform at least one of, increase a value of a third voltage atthe data line, and increase a value of a fourth voltage at the source.10. The apparatus of claim 9, wherein the memory control unit isconfigured to perform at least one of increase the value of the thirdvoltage at the data line and increase the value of the fourth voltage atthe source while the positive value of first voltage is decreased andbefore the first voltage reaches the ground potential.
 11. The apparatusof claim 9, wherein the memory control unit is configured to perform atleast one of increase the value of the third voltage at the data lineand increase the value of the fourth voltage at the source after thefirst voltage reaches the ground potential.
 12. The apparatus of claim9, wherein the memory control unit is configured to: decrease thepositive value of first voltage in the second stage of the operationuntil the first voltage reaches the ground potential; and to decrease anadditional value of the third voltage after the first voltage reachesthe ground potential.
 13. The apparatus of claim 9, wherein the memorycontrol unit is configured to: decrease the positive value of firstvoltage in the second stage of the operation until the first voltagereaches the ground potential; and decrease an additional value of thefourth voltage after the first voltage reaches the ground potential. 14.The apparatus of claim 9, wherein the first stage includes a write stageof the operation, and the second stage includes a write verify stage ofthe operation.
 15. The apparatus of claim 9, wherein the first stageincludes a read stage of the operation.
 16. The apparatus of claim 9,wherein the first stage includes an erase verify stage of the operation.17. A method of operating a memory device, the method comprising:applying a first voltage having a positive value to a control gate in afirst stage of an operation performed on a selected memory cell amongmemory cells of a memory cell string associated with the control gate,the memory cell string including a body coupled to a data line and asource; decreasing the positive value of the first voltage in a secondstage of the operation; applying, in the second stage, a groundpotential to first and second select gates associated with first andsecond select transistors, respectively, the memory cells coupledbetween the first and second select transistors; increasing a value of athird voltage at the data line while the ground potential is applied tothe first and second select gates in the second stage; and increasing avalue of a fourth voltage at the source while the ground potential isapplied to the first and second select gates in the second stage. 18.The method of claim 17, wherein: decreasing the positive value of thefirst voltage is performed until the first voltage reaches the groundpotential; and increasing the value of each of the third and fourthvoltages is performed before the first voltage reaches the groundpotential.
 19. The method of claim 17, wherein: decreasing the positivevalue of the first voltage is performed until the first voltage reachesthe ground potential; and increasing the value of each of the third andfourth voltages is performed after the first voltage reaches the groundpotential.
 20. The method of claim 17, further comprising: decreasingthe positive value of the first voltage until the first voltage reachesa ground potential; and decreasing the value of each of the third andfourth voltages after the first voltage reaches the ground potential.